Q1 (a) Draw the symbols of the following transistors and indicate conduction mode at
Vgs = 0V.

(i) NMOS enhancement mode
(ii) PMOS enhancement mode
(iii) NMOS depletion mode
(iv) PMOS depletion mode
(b) What are the advantages of Dynamic Precharge Logic over Static CMOS?
(c) What are the drawbacks of a transmission gate logic and what is required to
resolve them? Illustrate you answer with a transmission gate logic diagram.
(d) Tabulate the number of transistors required for the following logic circuit.

(i) NMOS
(ii) Transmission Gate
(iii) Precharge
(iv) Clocked CMOS
(v) CMOS
(vi) Pass Gate

Continued Overleaf
Q2 (a) Sketch the transistor-level schematic circuit diagram for a CMOS cell with the
following function, using the smallest number of transistors possible.
Z =A.(BC+D) [10]
(b) Determine the stack depth size the transistors using both the linear least deep
stack and the deepest stack method, taking into account the fact that µn = 3µp
(wpi = 3 Wni) and all transistors having the same gate length. [10]
(c) Draw a 2 bit half adder using XOR and AND logic gates and produce the
logic table. [5]
Q3 (a) A pipelined system architecture must be able to arbitrarily shift data one bit to
the left, one bit to the right, or not at all, in a single clock cycle. Sketch a
circuit that will do this using pass-transistor logic. You may assume that there
is an input and an output register associated with the device. [10]
(b) Derive Elmore delay expression of the chip interconnect model shown in
Figure Q3. [7]
Figure Q3
(c) Interconnect delay imposes serious speed limitations on CMOS routing of the
clock tree. Describe a clock tree design that, if correctly implemented, will be
free of clock skew. Sketch a diagram for your design and explain why and
where it will have no skew. [8]

Continued Overleaf
SECTION B: Attempt any TWO questions [50 marks]
Q4 (a) Most digital-to-analogue converter (DAC) architectures are based on the
popular resistor-ladder (R-2R) network. Draw the circuit diagram for a 3-bit
R-2R based DAC. [5]
(b) By analysis of the circuit you have drawn in Q4(a) show mathematically how
the input bits of the DAC relate to the analogue output voltage. [5]
(c) Another popular DAC architecture, the potentiometric DAC, is based on
selecting one tap of a segmented resistor string by a switch network. State the
key advantages of this type of DAC. Briefly explain how high resolution
converters exploit these advantages. [5]
(d) An alternative DAC architecture is based on a capacitor network. Draw the
circuit diagram for a 3-bit weighted-capacitor DAC, and briefly explain its
operation. [5]
(e) What are the advantages and disadvantages of using an R-2R DAC when
compared with weighted resistor or capacitor DAC architectures? [5]