VHDL代写 | ENSC252 Final Project #2
ENSC252 Final Project #2
Objective: Project #2 will provide students with a practical exercise in fault testing combinational circuits.
Lecture 18: Testing has been posted on Canvas. It will provide you with the necessary background and
methodologies required to test digital circuits and detect physical faults. In this project we will be using
stuck-at-fault testing to detect possible stuck-at-faults or bridge faults
Two combinational circuits will be randomly assigned to you in the form of .vho files. An email has been
sent to you with two links corresponding to your two assigned circuits. These two circuits may or may not
contain physical faults which have been manually injected into the system. Your assigned circuit diagram,
labelled as circuit1-4, may be viewed in the Appendix of this document. Note that these diagrams
represent the expected fabricated circuit without the presence of physical faults.
For each assigned combinational circuit:
1) Derive the minimum test set required to detect the presence of physical faults in the circuit.
2) Based on the minimum test set, determine if a fault exists in the circuit. In this case, you must create a
testbench for the circuit, insert your vho as the Device-Under-Test (DUT), and apply the minimum test set
as stimulus to determine whether a fault exists. Compare the actual circuit output to your expected
3) If a fault exists, conduct further testing to determine the exact location of the fault in the circuit.
Consider direct and indirect testing of wires. Create another testbench which clearly outlines your
verification methodology and reasoning. Provide your fault diagnosis i.e where the fault resides in the
circuit based on your testing methods.