MIPS代写｜CSEE W3827 – Fundamentals of Computer Systems HW #7

这是一篇美国的MIPS CPU设计cs作业代写

Topics: CPU Design Note that this homework has 5 problems on 2 pages.

(a) lw $t3, 40($s2)

(b) add $t3, $s2, $s1

(c) addi $t3, $s0, 37

(d) beq $s1, $s3, LABEL (where LABEL is 7 instructions before this beq instruction)

(e) j LABEL (where LABEL is the address 2088 in decimal).

Information provided in slides 106-127 from Lecture 11 might be helpful. Consider each case below separately.

(a) RegWrite= 0

(b) ALUOp0= 0

(c) ALUOp1= 1

(d) Branch= 1

(e) MemRead= 0

(f) MemWrite= 0

(g) RegDest= 1

(h) MemToReg= 0

(i) ALUSrc= 0

Hint: the circuitry that determines whether or not to take the branch (i.e., the conditional that feeds into the MUX making that determination) gets a bit more complicated

lw $s0, $s1, 13

For the above lw instruction, if the value in $s1 equaled A, then memory address A would be read, 13 would be added to this value, and the result of the sum would be stored in $s0.

sw $s0, $s1, 13

For the above sw instruction, if the value in $s1 equaled A, then memory address A would be written to with the value of 13 plus the value in $s0.

(a) How should the MIPS architecture be modifified to implement the above sw instruction (in place of the existing sw).

(b) How about to implement lw?

(c) Show how both be done simultaneously with a single ALU. The trick is to have MUX’s which choose the order of ALU and memory access.