Matlab代写｜EECS 511 2022 Final Assignment

这是一篇美国的matlab模数转换代码代写

In this assignment you will model a set-and-down SAR ADC with redundancy and noise shaping in MATLAB.

The ADC have differential input with a nominal input range 0 to 1 on the positive (vinp) and negative (vinn) inputs. The input common mode is 0.5. The ADC has a nominal resolution specified by numbits.

The input signal source is derived by from the vin vector. Both sine and ramp are possible depending on the variable sine_input_mode. Here is some sample code for generating the input signals:

if  sine_input_mode

fin=bin/samples; % samples is the total number of samples for the FFT

vin=input_amps(j)*sin(2*pi*fin*t);

vin=-0.5:.001:0.5; % ramp test

vinp=0.5+vin;

vinn=0.5-vin;

Samples are at 1 Hz. These variables are provided:

bin % The FFT bin number. Note the sample rate is 1Hz

input_amps % a vector or input amplitudes. The nominal maximum is 0.5

sine_input_mode % 1 for a sine input, 0 for a ramp

Use 216 samples for sine wave operation. However, allow an extra 10,000 samples at the beginning for the ADC to warm up.

Redundancy and set-and-down operation

Redundancy in a set-and-down ADC can be complicated. The sign bit can be especially tricky. We are providing some additional explanation to clarify things. (There are other ways of doing things but this approach is straightforward and consistent).

Your MATLAB program should work with an arbitrary coding scheme. We will provide some examples to you and also test your code independently with different coding scheme.

To explain things, we use this example for a 4 bit ADC: Weights = 6,4,2,2,1. This coding scheme has one redundant bit. The output code range is 0 to 15.

In the example below we go through the sequence of decisions and the corresponding comparator input voltages. In this test we apply a positive input of 0.501 and a negative input of 0.499 (i.e., the common mode is 0.5). We see that the MSB decision (bit 1) is 1. The process for calculating the set-and-down voltages is shown.

We calculate the overall decision value based on the weights. The key thing to notice is how the initial bit is calculated. Note that this gives an ADC range from 0 to 15. It is not signed.

bit1*6+ bit2*4 + bit3*2 + bit4*2 + bit5*1

1*6 + 0*4+ 0*2 + 1*2 + 0*1 = 8

To test the benefit of redundancy you test the conversion with an error in the first SAR step. The variable first_step_error contains this error. This error can be thought of as an error in the first comparison (e.g.due to comparator offset or settling). All other comparisons are ideal.

The data .mat file provided will have the following variables related to redundancy:

numbits % the nominal number of bits for the ADC

redun % extra bits for redundancy. This is 0 for binary coding

next_range_mag_arr % Vector of weights. Does not include termination weight

first_step_error % Error in first comparison. All other comparisons are ideal

You should use the capacitor DAC to generate the residue. As mentioned in class this will require an additional switching of the DAC after the final bit trial. The residue is the difference between

The following variables are related to the noise-shaping operation:

ns % ns=1 for noise shaping, and ns=0 for no noise shaping (i.e., no EF)

OSR % oversampling ration

EF_gain % error feedback gain, ideally = 1

Your code should begin by loading the settings .mat file. The code should ask for the name of this file.Here’s some sample code for this purpose:

test_data_file = input(‘Please input the name of the test data file: ‘,’s’);load(test_data_file)

There are two test scenarios: sine wave testing and ramp testing. The requirements differ for each so please read carefully:

o input_amps is just a single number

o Plot the FFT, use a log frequency axis

o Identifying the bandwidth with a vertical line

o Title the graph with the SNDR

o On a separate figure, plot the residue versus vin (For samples from 10000 to 20000)

o input_amps is a vector

o Provide a single graph of SNDR vs input_amps

o Use a log horizontal axis

o Report the maximum SNDR

o Digital output vs differential input voltage

o Residue (generated by DAC) plotted versus differential input voltage

o In some cases we will use code plagiarism checking.

o Commented code

o Outputs and plots for the test settings provided

o There will be 3 test setting files provided.

o Use 1 page for each run, showing plots, settings, results and the name of the test files.

o Your code should be a single self-contained .m file.