计算机代写｜ECE 6913 INET Quiz 2 Instructions

这是一篇美国的计算机体系架构限时测试计算机代写

This Quiz has 4 problems, each with multiple parts. Please attempt all of them. Please show all work. Please write legibly

1. Please be sure to have 10- 15 sheets of white or ruled Paper, a Pen/Pencil & Eraser

2. Please write down your solutions on 8.5 x 11 sheets of white paper, single-sided with your name printed in top right corner of each sheet and with Page Number and Problem number identified clearly on each s heet

3. Please stop working on your Quiz at 10:30 AM – you have 10 minutes to scan/take pictures of each sheet and upload them as completed PDF assignment to NYU Classes by 10:40 AM – you may use any of several smartphone apps to integrate your scans/ pictures of sheets into a PDF file.

4. Please take pictures of each sheet and upload the PDF of all sheets after checking you have all sheets in the right order by 10:45 AM latest.

5. You may use iPAD to write down your solutions directly rather than on paper

6. Portal will close at 10:45 AM not allowing upload of your quiz after 10:45 AM

Problem 1. Y our Company describes their latest Processor with the following features:

You are considering adding a peripheral to the system, and you want to know how much of the memory system bandwidth is already used.

1.1 Calculate the percentage of memory system bandwidth used assuming the cache is W rite Back.

1.2 Calculate the percentage of memory system bandwidth used assuming the cache is Write Through.

Please be sure to state your assumptions and show all work

Problem 2. One difference between a write-through cache and a write-back cache can be in the time it takes to write. During the first cycle, we detect whether a hit will occur, and during the second (assuming a hit) we actually write the data.

Let’s assume that 50% of the blocks are dirty for a write -back cache. For this question, assume that the write buffer for the write through will never stall the CPU (no penalty). Assume a cache read hit takes 1 clock cycle, the cache miss penalty is 50 clock cycles, and a block write from the cache to main memory takes 50 clock cycles. Finally, assume the instruction cache miss rate is 0.5% and the data cache miss rate is 1%. Assume that on average 26% and 9% of instructions in the workload are loads and stores, respectively.

2.1 Estimate the performance of a write-through cache with a two-cycle write versus a write-back cache with a two- cycle write.