计算机代写｜COEN 316 Computer Architecture Lab 2 Register File

这是一篇来自美国的关于计算机架构实验室2寄存器文件的计算机代写

Introduction

In this lab, a multi-port register fifile will be designed. The following VHDL entity specifification is to be used for the design of the register fifile:

— 32 x 32 register file

— two read ports, one write port with write enable library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity regfile is

port( din : in std_logic_vector(31 downto 0);

reset : in std_logic;

clk : in std_logic;

write : in std_logic;

read_a : in std_logic_vector(4 downto 0);

read_b : in std_logic_vector(4 downto 0);

write_address : in std_logic_vector(4 downto 0);

out_a : out std_logic_vector(31 downto 0);

out_b : out std_logic_vector(31 downto 0));

end regfile ;

The register fifile consists of 32 registers (R0-R31), each register consisting of 32 bits. The entire register fifile can be reset (each register cleared to 0) by asserting the asynchronous active-high reset input. There are two read ports (out_a and out_b). The 5 bit addresses presented on the input ports read_a and read_b determine which of the 32 registers are made available at the output ports out_a and out_b respectively. For example, if read_a = “00101” and if read_b = “01111” the contents of register R5 is outputted on out_a and register R15 is outputted on the out_b port. Note that the reading is done asynchronously (i,.e. independent of the clock input). The register fifile contains a single input port (din) which is used to provide 32 bit data to be written into a specifific register. The 5 bit address presented on the write_address input determines which of the 32 registers is to be written to. The writing of the data to the specifified register is synchronous (i.e. occurs with a rising clock edge) and is also controlled by the write signal which is an active high signal (in order for a write to occur, the write signal must be ‘1’ and the clock input must change from ‘0’ to ‘1’ ).

Figure 1 gives the block diagram of the register fifile showing its input and output ports.

Procedure

Design the register fifile using VHDL. You may use any style of VHDL (i.e. structural with port maps, processes, CSA statements, etc.) as you wish. Simulate your design with the Modelsim simulator to verify correct functioning for all the possible operations supported by the register fifile for typical input values. Synthesize your VHDL code with the Xilinx Vivado tools.

Board Implementation

Similar to Lab 1, only a subset of the various input and output ports will be mapped to switches

and LEDs via a .xdc fifile. You are to simulate the full 32-bit design and to create a “board wrapper” VHDL fifile for implementation. Use the following entity specifification for the “board wrapper” VHDL code:

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity regfile is

port( din_in : in std_logic_vector(3 downto 0);

reset : in std_logic;

clk : in std_logic;

write : in std_logic;

read_a_in : in std_logic_vector(1 downto 0);

read_b_in : in std_logic_vector(1 downto 0);

write_address_in : in std_logic_vector(1 downto 0);

out_a_out : out std_logic_vector(3 downto 0);

out_b_out : out std_logic_vector(3 downto 0));

end regfile ;

Requirements

force din X”FAFA3B3B”

Similar notation may be used within a DO fifile. Within the Waveform window, one can select a particular signal and specify the radix as hexadecimal. This will allow for easier understanding of the displayed values.

You are to test your register fifile design for several different input combinations. Write values into several registers, then read out the values. Document clearly in the lab report (with the use of a table or other means) the test cases that you have selected and the expected values and whether your design simulates as expected. Your test inputs should fifirst reset all the registers, and then proceed to write values into certain registers and then read out the registers which you have written into and also read out other registers which have NOT been written into.