编程代写｜Notes and Tips for CMPEN331 Final Project

这是一篇来自美国的关于最终项目的注释和提示的编程代写

As always, start early!
The Final Project is longer than the labs and about the same difficulty
LATE SUBMISSIONS WILL NOT BE ACCEPTED FOR THE FINAL PROJECT AND WILL RECEIVE A ZERO
This video assumes you have completed Lab 5
If you have not already completed Lab 5, You need to do so before starting the Final Project
The Bonus for the final project will be detailed in a separate video
However, you should watch this video first as the final project bonus video builds off of this video

Labs 3 through 5, along with the final project,consists of implementing different stages/features of our five stage MIPS pipeline.
The main structure of the five stages will be implemented through the labs, and the final polish and functionality will be implemented in the final project. There is also a bonus for the final project that implements additional instructions.
The bonus on final project is extra credit, I highly recommend that all of you try the bonus if you have time.
Lab 3: Stages 1 and 2 (Instruction Fetch,Instruction Decode)
Lab 4: Stages 3 and 4 (Execution, Memory Access)
Lab 5: Stage 5 (Writeback)
Final Project: Forwarding Behavior
Final Project Bonus: Control Transfer
Instruction Implementation (branch/jump instructions).

FORWARDING

Values that are available in the pipeline (i.e. not yet written to the regfile) and needed in the ID stage can be forwarded to reduce stalls and improve performance.
This is done with two 4:1 multiplexers and some extra logic in the Control Unit Stalls will still be needed in some cases, which will be done with some more logic within the Control Unit

IMPLEMENTATION

Once we’ve completed our processor, we will generate an implementation that can be written to an FPGA
We first need to prepare our design for this(mainly accommodating I/O limits within the FPGA)
Note: This step is not needed if you plan on doing the bonus

New Instructions:
We will be adding the following instructions to our control unit:
SUB
AND
OR
XOR
These instructions will all use the same control signals as ADD with the exception of the aluc signal,which will vary between these instructions
There are no set values for what the aluc should be set to for each operation, use whatever works best/makes the most sense to you
Stalling:
We will need to stall if we have a load word instruction that is immediately followed by an instruction that uses the value being loaded by the load word instruction.
wpcir is our stall signal. It is active-low, meaning the pipeline registers stall if wpcir is 0 (rather than stalling if wpcir is 1).
New internal register regusage: 1-bit wide, set to 1 if rs or rt is being read
Unless you’re doing the bonus, this signal will be set to 1 for all instructions
pseudocode for our wpcir signal (this goes outside of your case statement):
if (
exe stage writes to regfile and
exe stage writes from memory to register and
exe stage destination register is not 0 and
regusage is 1 and
(exe stage destination register equals either rs or rt)
)
begin
wreg is set to 0
wmem is set to 0
wpcir is set to 0
end else begin
wpcir is set to 1
// don’t set wreg and wmem here
end

Forwarding:
We need to forward data if we have an instruction that uses a value that is in the pipeline but not yet written back into the register file
We could use stalling to handle this, but forwarding allows us to not stall and execute instructions faster at the cost of more hardware
Control Signals for forwarding will be based on the following pseudocode (this goes outside of your case
statement):
if (
exe stage writes to regfile and
exe stage destination register is not zero and
exe stage destination register equals rs and
exe stage memory to register is zero
) fwda is set to 1
else if (
mem stage writes to regfile and
mem stage destination register is not zero and
mem stage destination register equals rs and
mem stage memory to register is zero
) fwda is set to 2
else if (
mem stage writes to regfile and
mem stage destination register is not zero and
mem stage destination register equals rs and
mem stage memory to register is one
) fwda is set to 3
else fwda is set to 0
repeat above for fwdb, but replace every “rs” with “rt”

ALU
Your ALU should be modified to support the new aluc signals/operations. This should be trivial.

Program Counter and IF/ID Pipeline Register

These modules will have a new 1-bit input: wpcir
This input simply is a write-enable. If it is zero, writes to these modules do not occur. This change should be trivial.

Instruction Memory

The five instructions in instruction memory will be replaced by the following instructions:
add $3, $1, $2
sub $4, $9, $3
or $5, $3, $9
xor $6, $3, $9
and $7, $3, $9
These will replace the load word instructions along with the one add instruction