作业代写｜ECE 6443 Homework Assignment 4
1. For the schematic shown below determine:
(i) Maximum Register-Register delay
(ii) Minimum Register-Register delay
(iii) Setup time at ‘A’ (time A has to be stable before CK makes transition)
(iv) Minimum Cycle time
(v) Hold time at ‘A’ (time A has to be stable after CK makes a transition)
(vi) Largest CLK → Y delay
(vii) At minimum cycle time, Setup time violation?
(viii) Hold time violation?
Tsu = 3ns
Thd = 4ns
Tc2q = 5ns
The setup check can be mathematically expressed as:
where Tlaunch is the delay of the clock tree of the launch flip-flop UFF0, Tdp is the delay of the combinational logic data path and Tcycle is the clock period. Tcapture is the delay of the clock tree for the capture flip-flop UFF1.
In other words, the total time it takes for data to arrive at the D pin of the capture flip-flop must be less than the time it takes for the clock to travel to the capture flip-flop plus a clock cycle delay minus the setup time.
Since the setup check poses a max constraint, the setup check always uses the longest or the max timing path. For the same reason, this check is normally verified at the slow corner where the delays are the largest.
The report shows that the launch flip-flop (specified by Startpoint) has instance name UFF0 and it is triggered by the rising edge of clock CLKM. The capture flip-flop (specified by Endpoint) is UFF1 and is also triggered by the rising edge of clock CLKM. The Path Group line indicates that it belongs to the path group CLKM. All paths in a design are categorized into path groups based on the clock of the capture flipflop. The Path Type line indicates that the delays shown in this report are all max path delays indicating
that this is a setup check. This is because setup checks correspond to the max (or longest path) delays through the logic. Note that the hold checks correspond to the min (or shortest path) delays through the logic.
The Incr column specifies the incremental cell or net delay for the port or pin indicated. The Path column shows the cumulative delay for the arrival and the data required paths.